A great article published in IEEE Spectrum outlines the current state of semiconductor transistors and Moore’s Law and the situation looks tense. To keep up the pace of release new product families with a new process every 18 to 24 months, the chip industry has been struggling to deliver on denser chips with twice the power and efficiency—while marketers have co-opted the naming process to render it meaningless.
“Nobody knows anymore what 16 nm means or what 14 nm means.” -Chenming Hu, the coinventor of the FinFET
FinFET is the name for the state-of-the-art three-dimensional switcher that the industry is hoping might carry on pacing Moore’s Law into the next generation. But those same chips come with a deception; as the article points out, Intel’s current state-of-the-art 22-nm chips have FinFET transistors with gates that are 35nm and fins that are just 8nm wide.
Complicating matters is that the sheer density and power levels on these state-of-the-art chips have forced designers to compensate by “adding error-correction circuitry, redundancy, read- and write-boosting circuitry for failing static RAM cells, circuits to track and adapt to performance variations, and complicated memory hierarchies to handle multicore architectures”—which all add area.
So even though the node names continue to drift downwards, and the density continues to double from generation to generation, the names no longer match the size of any specific chip dimension.
The practice of attaching measurements to chip generations has “been hijacked by marketers to an enormous extent,” one chip-design expert told me.
Plus the transition from old to new no longer provides the kind of payoff, in cost or performance, that it used to, according to the article. There just hasn’t been time to explore design technologies that could cut down on power or boost performance. “When you’re on that kind of schedule, you don’t have time to optimize things,” says Andrew Kahng, a professor at the University of California in San Diego and expert on high-performance chip design quoted in the article.
(Intel’s upcoming Quark SoC. Image via Intel)
It may be time for chip makers to give up the ghost here and focus on optimizing and refining the technology already developed, instead of continuing to chase after a futile goal. GlobalFoundries, the world’s second-biggest chip-making foundry, has decided to put a stop to the shrink and next year will be putting out their first-gen FinFET 14-nm chips with the same wiring density used in its 20-nm chips. These new chips will still offer roughly a generation’s-worth jump in performance and energy saving over its current 20-nm chips, however the cellphone makers have been very vocal about not getting a shrink along with the performance improvement.
Though it will be discouraging to give up the promise of Moore’s Law, it might be necessary in order to ensure the success of chip manufacturers and the integrity of their products.
Read the full article here; I promise you it’s fascinating.